A Scalable VLSI MIMD Routing Cell

It is a well known fact that full custom designed computer architectures can achieve much higher performance for specific applications than general purpose computers. This performance has to be paid for: a long design trajectory results in a high cost-performance ratio. Current VLSI design and compilation tools however, make semi-custom designs feasible with greatly reduced costs and time to market. This paper presents a scalable and flexible communication processor for message passing MIMD systems. This communication processor is implemented as a parametrisized VLSI routing cell in a VLSI compilation system. This cell fits into the SCARCE RISC processor framework [1], which is an architectural framework for automatic generation of application specific processors. By use of application analysis, the cell is tuned to the specific requirements during silicon compilation time. This approach is new, in that it avoids the general performance penalty paid for required flexibility.